Qualification of semiconductor devices usually involves a plurality of tests, including tests at elevated temperatures. Such tests are referred to with different names, such as High Temperature Operating Life Test (HTOL), reliability test and stress test. Without limiting us to a specific type of test, we will briefly refer to any of these tests as HTOL tests. The test conditions may depend on the specific semiconductor device and its intended application. The common method to test semiconductor devices during prolonged operation at an elevated temperature is to operate the semiconductor device under test in a convection heating chamber, such as an oven, that is operated during the test to provide a user-defined heat-controlled convection to the semiconductor device under test (briefly referred to as DUT). Such known method may however have disadvantages. For example, a HTOL test may require using temperatures higher than the maximum temperature of the available oven, e.g. requiring testing at 150° C. while the available oven is only able to provide 135° C., thus needing to acquire a new oven. As another example, another HTOL test may require testing at a plurality of temperatures, e.g. at 135° C. and 150° C. As another example, another HTOL test may require testing at a one or more temperatures relatively little above typical ambient temperatures, such as e.g. in a range of 25° C.-50° C.
FIG. 1 schematically shows an example of a prior art heating system 300P. FIG. 1 shows the prior art heating system while an HTOL test is performed on a semiconductor device under test 100. The heating system 300P comprises an oven having a convection heating chamber 310. The convection heating chamber 310 is operable to provide a user-defined heat-controlled convection to the semiconductor device under test 100 (DUT) placed in the convection heating chamber 310.
The user-defined heat-controlled convection corresponds to an oven air flow heating the semiconductor device under test 100. Hereby, the semiconductor device under test 100 may be tested while being operated in an environment of a pre-determined temperature, e.g. at 135° C.
The semiconductor device under test 100 is temporary received in a socket 212 on a test board 200P. The socket 212 comprises electrical connections 211 connecting signal pins 101 of the semiconductor device under test 100 via a signal conductor 210 provided on a top side 201 of the test board 200P to a control system 400P. A contact area 222 is provided in the socket 212. The contact area 222 contacts an expose pad 102 of the semiconductor device under test 100 when the semiconductor device under test 100 is received in the socket 212. A pin 220 extends through a through-hole 205 extending through body 203 of the test board 200P to a supply line 214 provided on a bottom side 202 of the test board 200P. The supply line 214 is connected to a supply voltage.
The control system 400P provides when in operation control signals 410P via the signal conductor 210 to the signal pins 101 of the semiconductor device under test 100 and for operating the semiconductor device under test 100 with electrical operating conditions. The control system 400P further controls the supply voltage provided to the expose pad 102 of the semiconductor device under test 100 via the supply line 214 and the pin 220 contacting the expose pad 102.
The control system 400P further controls the convection heating chamber 310 via a convection control signal 402P to provide a user-defined heat-controlled convection to the semiconductor device under test 100. Alternatively, the convection heating chamber 310 is controlled independently to provide the user defined heat controlled convection.
A user may thus perform a High Temperature Operating Life Test (HTOL) on the semiconductor device under test 100 at a temperature defined by user-defined heat-controlled convection by operating the semiconductor device under test 100 for a prolonged period at the temperature defined by user-defined heat-controlled convection.